1. Field of the Invention
The present invention relates to a semiconductor device formed on a semiconductor substrate, and a method of manufacturing the same.
2. Description of the Background Art
One example of a conventional semiconductor device is a P-channel MOS (Metal Oxide Semiconductor) transistor formed on an SOI (Silicon On Insulator or Semiconductor On Insulator) substrate.
In the SOI substrate, a support substrate such as a silicon substrate, an oxide film layer and an SOI layer are stacked in this order. The P-channel MOS transistor comprises a gate electrode, a gate insulating film and P-type source/drain active layers.
In the formation of the P-channel MOS transistor on the SOI substrate, a multilayer structure of the gate electrode and the gate insulating film is formed on the surface of the SOI layer, and the source/drain active layers are formed in the SOI layer to sandwich the gate electrode.
A conventional semiconductor device has generally been configured such that a direction of a channel between source and drain of a MOS transistor is aligned parallel to a <110> crystal direction (orientation) of a semiconductor wafer.
However, if the channel direction is aligned parallel to a <100> crystal direction instead of being parallel to the <110> crystal direction, transistor characteristics can be varied. More specifically, it has been known that the channel direction aligned parallel to the <100> crystal direction results in an approximately 15-percent improvement in current drive capability of a P-channel MOS transistor and also in a reduced short channel effect (see Japanese patent publication No. 2002-134374).
The reason for improved current drive capability is considered to be higher hole mobility in the <100> crystal direction than in the <110> crystal direction, and the reason for reduced short channel effect is considered to be a smaller diffusion coefficient of boron for the <100> crystal direction than for the <110> crystal direction.
Thus, also for formation of the P-channel MOS transistor on the SOI substrate, the channel direction therein should be aligned parallel to the <100> crystal direction of the SOI layer. For this, for example an SOI substrate should be employed which is formed such that a <100> crystal direction of the SOI layer on the surface side is aligned with a <110> crystal direction of the support substrate, and on the surface of that SOI substrate, a device such as the P-channel MOS transistor should be formed.
In the case of (100) wafers, a {110} crystal plane is a cleavage plane. Thus, if a <100> crystal direction of a wafer for the SOI layer is aligned with a <110> crystal direction of a wafer for the support substrate for bonding, a complete whole wafer can, at the time of cleavage for test and research, be cleaved along the cleavage plane of the wafer for the support substrate which makes up a large portion of the complete wafer thickness. This brings the advantage that a section of the support substrate along the <110> crystal direction and a section of the SOI layer along the <100> crystal direction can be exposed at the same time.
Such a technique of aligning the <100> crystal direction of the SOI layer with the <110> crystal direction of the support substrate has been disclosed in, for example, Japanese patent publications Nos. 2002-134374 and 7-335511.
Other prior art reference information relating to the invention of this application includes the following unpatented references: (1) Y. Hirano, et al., “Bulk-Layout-Compatible 0.18 μm SOI-CMOS Technology Using Body-Fixed Partial Trench Isolation (PTI),” USA, IEEE 1999 SOI conf., p.131–132; (2) S. Maeda, et al., “Suppression of Delay Time Instability on Frequency Using Field Shield Isolation Technology for Deep Sub-Micron SOI Circuits,” USA, IEDM, 1996, p.129–132; and (3) L.-J. Hung, et al., “Carrier Mobility Enhancement in Strained Si-On-Insulator Fabricated by Wafer Bonding,” USA, 2001 Symposium on VLSI Technology, p.57–58.